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In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs at the three enable inputs select one of eight output lines.
Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A line decoder can be implemented without external inverters and a line decoder requires only one inverter.
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Datasheet Texas Instruments SN74HC138N
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3-Line To 8-Line Decoders/Demultiplexers
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